Design and FPGA Implementation of a Low-Power CNN Accelerator for Edge AI Applications
DOI:
https://doi.org/10.15662/IJEETR.2026.0802079Keywords:
Bit Separable Multiplier, Convolutional Neural Network, Energy Efficient Hardware, Field Programmable Gate Array, Radix-4 Booth Encoding.Abstract
Convolutional Neural Networks (CNNs) have become the cornerstone of modern edge AI applications, enabling real-time inference for vision, speech, and IoT systems. However, their deployment on resource-constrained devices remains limited by high computational cost and energy consumption, primarily due to the intensive multiply-accumulate (MAC) operations in convolutional layers. This work presents the design and FPGA implementation of a Bit-Separable Radix-4 Booth Multiplier tailored for power-efficient CNN accelerators. Unlike conventional Booth multipliers, the proposed design partitions operands into separable bit-groups to enhance parallelism while minimizing switching activity. The Radix-4 encoding reduces the partial product count by half, while bit-separability enables selective activation of sub-multipliers, thereby reducing dynamic power without sacrificing throughput. The architecture integrates approximate computing concepts by exploiting error-tolerant properties of CNNs, allowing operand gating and truncated accumulation in less significant bit segments. To further enhance energy efficiency, the multiplier is embedded into a tiled systolic MAC array with weight-stationary dataflow, reducing off-chip memory accesses. FPGA synthesis results on the Xilinx Zynq-7000 xc7z020 device demonstrate significant reductions in dynamic power consumption and LUT utilization compared to standard Booth and array multipliers, while maintaining competitive inference accuracy across benchmark CNN models. The proposed multiplier achieves up to 80% power savings and 30% resource efficiency with negligible accuracy loss (<1%) when used for quantized CNNs on edge workloads. This work highlights that Bit-Separable Radix-4 Booth multipliers can serve as the core arithmetic engine for low-power CNN accelerators, enabling scalable, energy-efficient, and high-performance edge AI deployments.
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